The present invention disclosed herein relates to a transistor, and more particularly, to a self-alignment transistor and a method of fabricating the same.
Transistors are widely used in various electronic device fields for a variety of purposes. For example, transistors are used as switching devices, driving devices, photo sensing devices, and other various components of electronic circuits. Transistors are classified into top gate structure transistors and bottom gate structure transistors. In the top gate structure, a source/drain electrode and a semiconductor layer is at the bottom and a gate insulating layer and a gate electrode are disposed thereon.
Transistors typically have a structure in which a source/drain overlaps a gate partially. In this case, parasitic capacitance occurs at a portion where the source/drain overlaps the gate, thereby slowing down operating speed.